An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS

Abstract

This brief presents the design of a low-power receiver (RX) with an adaptive equalizer and an offset cancellation scheme. The proposed adaptive offset cancellation (AOC) engine removes the random DC offset of the data path by examining the sampled data and edge outputs of a random data stream. In addition, a shared-summer decision-feedback equalizer in a half-rate structure is incorporated to reduce power dissipation and hardware complexity of the adaptive equalizer. A prototype chip fabricated in 40 nm CMOS technology occupies an active area of 0.083 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Thanks to the AOC engine, the proposed RX achieves the BER of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> in a wide range of data rates: 1.62-10 Gb/s. The proposed RX consumes 18.6 mW at 10 Gb/s over a channel with 27-dB loss at 5 GHz, exhibiting a figure-of-merit of 0.068 pJ/b/dB.