AN ADAPTIVE NOISE CANCELER IMPLEMENTED WITH CMOS ANALOG TECHNOLOGY

Abstract

A fully analog implementation of an adaptive noise canceler is presented, including design, simulation, and test results of the fabricated chip. The prototype chip was fabricated using 2-µ CMOS P-Well technology on a 4.0 mm2 die and uses ±5 V power supplies. The static power dissipation is 276 milliwatts. Analog signal processing techniques are used to realize an adaptive system based upon a finite impulse response (FIR) filter and least mean squares (LMS) adaptive algorithm. The circuit is tested as an adaptive noise canceler, where a signal corrupted by noise is the input. The circuit adaptively converges to cancel the noise to produce an output that is the best LMS estimate of the signal. The circuit could be used for other real-time adaptive filter applications or for realizing an on-chip learning algorithm. The implementation illustrates the advantages of an analog system with no requirements for A/D and D/A converters, reduced size of circuit subsystems (e.g. multipliers), and the relatively fast convergence.