Abstract
A digital carrier recovery (CR) loop with an adaptive loop bandwidth for rapid carrier frequency offset acquisition and low steady-state jitter is proposed in this paper. In addition to the traditional CR functional blocks, the presented carrier synchronizer consists of a tracking-status detector and a loop bandwidth controller. The tracking-status detector monitors the frequency-estimate signals output from the frequency-tracking (integral) branch of the loop filter, detecting whether the frequency offset is locked or not. Then, by adjusting the loop bandwidth in response to the detected result, the convergence time of the acquisition-state and the carrier jitter in the steady-state can be reduced. The new scheme, implemented by FPGAs, has been successfully applied to a 256-QAM baseband digital receiver and also inter-operated with a commercial CMTS. The SNR performance can be improved up to 3 dB only at the expense of 3% hardware area of a Virtex-II-2000 FPGA for this proposed architecture.
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