An active learning scheme using support vector machines for analog circuit feasibility classification

Abstract

This paper presents a new active learning scheme using support vector machines (SVMs) and its application in identifying the feasibility design space of analog circuit. The proposed methodology uses a committee of SVM classifiers to exclude a large portion of the entire design space and samples only the feasibility region and its neighboring. We also introduce three accuracy metrics due to the extreme sparsity of the feasibility design space in the entire design space. Experimental results show that the three accuracy metrics of the final constructed classifier are much better than those of a classifier constructed by a passive learning scheme which samples the entire design space uniform randomly.