An Accurate Two-Port De-Embedding Technique for RF/Millimeter-Wave Noise Characterization and Modeling of Deep Submicrometer Transistors

Abstract

An accurate and simple noise de-embedding technique is proposed for high-frequency noise characterization of transistors. It is demonstrated on 0.13-μm CMOS devices for up to 80 GHz. The proposed technique adopts a generalized two-port fixture model in conjunction with a set of shielded based structures, which enable simple de-embedding of fixture parasitic for up to the Metal 1 level. Unlike other methods, it is capable of simultaneously accounting for the parasitic effects of probe to pad contact impedances and metal finger parasitic while using only three dummy test structures. Also, it is designed to accommodate nonsymmetry between bond pad parasitic elements at two-port without consuming additional silicon area. This corresponds to a reduction in noise de-embedding error, which increases along the frequency domain (6% of NFmin at 80 GHz). Meanwhile, underestimation of metal finger parasitic by conventional techniques has lead to degradation in noise performance (NFmin) of 0.13-μm CMOS transistors by more than 3.5 dB at 80 GHz. Further validation results from extracted gate capacitance and transistor gain performance provide solid support to the proposed de-embedding technique.