Abstract
This paper accurately models the crosstalk effects in a CMOS-gate-driven coupled RLC interconnects using the nth power law model and finite-difference time-domain (FDTD) technique. The propagation delay, peak crosstalk voltage, and peak voltage timing on victim line of coupled-multiple lines are observed and compared to HSPICE simulation results for the global interconnect length at 32 nm technology node. The numerical results illustrate that the proposed model accurately estimates the performance parameters of driver interconnect load system. An average error of less than 2% is observed in estimation of peak crosstalk voltage and its timing. The proposed model can be extended for coupled n lines and useful for the evaluation of signal integrity, issues of EMI, and EMC of on-chip interconnects.
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