An Accurate Analysis of Phase Noise in CMOS Ring Oscillators

Abstract

We present an accurate analysis of phase noise in ring oscillators, where each stage in the ring is a CMOS inverter loaded by a capacitance. Closed-form phase noise expressions are obtained in both 1/ ${f} ^{{2}}$ and 1/ ${f} ^{{3}}$ offset frequency regions, displaying an excellent agreement with numerical simulations using either ideal Verilog-A MOS models (allowing theoretical predictions to be tested with exactly the same assumptions under which they were derived), or commercial BSIM4 MOS models.