An accelerated reliability test for retention after fatigue in ferroelectric memory devices

Abstract

A prime advantage of ferroelectric nonvolatile memories over floating gate EEPROMs is the ability to rewrite data up to 1010 times without loss of functionality. This paper will demonstrate that data retention is not constant with increasing write cycles but degrades according to the number of switching cycles. An accelerated stress test to characterize the degradation in retention as a function of fatigue for production lots of product has been developed and used at Ramtron as a qualification test for 16K serial and 64K parallel memory devices. In this test, entire rows of memory cells with common bottom electrodes are alternately written with ones and zeros using standard semiconductor burn-in hardware with modified software. The use of complete rows allows for the separation of the memory array into fatigued and unfatigued portions which would not be possible if 1 byte or any portion of a row were fatigued due to the read/restore scheme which the entire row will see for any access within the row. Typically four adjacent rows of each device are chosen as the fatigued sample, while the rest of the memory is used as a control (unfatigued). Retention testing is performed after fatigue stress and the location of failing bits is tabulated for fatigued/ unfatigued failed bits.