An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications

Abstract

A 3-D graphics SoC, with a multi-layer advanced microcontroller bus architecture (AMBA) system, full pipelined hardware 3-D graphics accelerator, and clock/power management is proposed as a 49-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die for 180-nm CMOS technology. This system-on-chip (SoC) minimizes power consumption with a clock/power management unit according to its operation mode and applications. The 3-D graphics accelerator has a full pipelined architecture which improves full 3-D graphics performance to 8M polygons/s and consumes 108 mW at 100 MHz and 1.8 V. The LCD bypass mode and power-down mode consume 4.32 mW and 180 uW, respectively. The 3-D graphics accelerator also supports stereoscopic 3-D function with an alternative left-right drawing method and achieves a 59% improvement in 3DG performance compared to previous work.