An 8GHz first-order frequency synthesizer based on phase interpolation and quadrature frequency detection in 65nm CMOS

Abstract

A low-power high-speed frequency synthesizer in 65nm CMOS is presented. The design features a novel architecture combining an LC quadrature VCO, two sample-and-holds, a phase interpolator, digital coarse-tuning and a novel quadrature frequency detection technique for fine-tuning. The system works based on injecting the rising edges of reference clock. The architecture has first-order dynamics, eliminating jitter accumulation. Functionality of the frequency synthesizer was validated between 8-9.5GHz, LC VCO's range of operation. The output clock at 8GHz has an integrated rms jitter of 0.5ps and peak-to-peak periodic jitter of 2.9ps. The reference spurs are -64.3dB below the carrier frequency. The system consumes 2.49mW from a 1V supply at 8GHz.