Abstract

This paper presents an energy-efficient forwarded-clock receiver in 40nm CMOS process. The receiver adopts injection-locked ring oscillator (ILRO) to implement jitter filtering and phase deskew. The proposed cascaded ILROs enable our receiver to maintain a constant jitter tracking bandwidth (JTB) for good jitter tolerance and generate accurate quadrature clocks for quarter-rate sampling. The first-stage ILRO is used to control the JTB and filter out the high-frequency clock jitter that cannot track the data jitter. The second-stage ILRO is injected by the first one's outputs to generate precise quadrature clocks for phase shifting and deskew. The simulation results show our receiver can work at 8Gb/s and consume only 6mW under a 0.9V power supply voltage. The JTB can be controlled up to 260 MHz with a variation less than 20 MHz and the quadrature phase error is minimized to 1°.

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