An 8-bit 80-MS/s Fully Self-Timed SAR ADC with 3/2 Interleaved Comparators and High-Order PVT Stabilized HBT Bandgap Reference

Abstract

This paper presents the design of a fully self-timed 8-bit 80-Ms/s single-core SAR ADC with interleaved comparators and a high order compensated opamp-less bandgap reference. A 3/2 interleaving algorithm was designed for better SFDR performance, where two of the three comparators are orderly chosen for interleaving in each conversion while offset calibration is applied to the idle comparator. Asynchronized SAR logic with a DAC settling timer is designed for fully self-timing of the ADC. The ADC was designed with a PVT stabilized on-chip reference source which promises a stable reference for the ADC at extreme temperature environments such as aerospace exploration or quantum computing. Technique for compensating the temperature coefficient (TC) of a bandgap reference (BGR) using temperature characteristics of transistor's current gain β is proposed. Measured results show 42.8dB SNDR, 56.8 dB SFDR and −53.3dBc THD for the proposed SAR ADC, drawing 1.07mW from a 1.1v supply. Measured average TC of the HBT proposed BGR is 23ppm/°C and 39 ppm/°C over the commercial (0∼70°C) and space (−260∼125°C) temperature ranges, respectively. The BGR reaches PSRR of −50dB at 1MHz, and −38dB at 1GHz. The entire chip was implemented on 0.13um 8HP SiGe process with an active area of 0.2952 mm2.