An 8b 80MSample/s pipelined ADC with background calibration

Abstract

Conventional pipelined ADCs with redundancy and digital correction have linearity limited by the gain accuracy of the interstage amplifiers or the linearity of the D/A subconversions. With a fully differential 1.5 b/stage architecture, the D/A subconverters can in principle be inherently linear, and the main limitation stems from the interstage gain accuracy. Besides the error caused by finite-op-amp gain and capacitor mismatch, the linear portion of the incomplete op-amp settling can also be modeled as an interstage gain error. One way to compensate for interstage gain errors is to adjust the reference voltage from each stage to the next so that the ratio of the reference in one stage to the corresponding value in the previous stage is equal to 1+/spl epsi/, where /spl epsi/ is the gain error between the stages. This pipelined ADC uses monolithic calibration to adjust the reference voltages of the first two stages in the background during normal ADC operation to compensate for gain errors in the first two interstage amplifiers. Calibration is potentially useful even at an 8b level because it allows the use of small capacitors and low op-amp gain, reducing power dissipation and the minimum required supply voltage and increasing the maximum speed in a given technology. The key contributions here are the use of background calibration to improve the linearity of a pipelined ADC and the implementation of these techniques with the ADC on one CMOS IC.