An 86 K component bipolar VLSI masterslice with a 290-ps loaded gate delay

Abstract

A very large-scale integrated (VLSI) bipolar masterslice has been demonstrated. This masterslice has a loaded three-input ECL gate delay of 290 ps and an unloaded gate delay of 164 ps at a power dissipation of 1.5 mW/gate. It is fabricated by using 1.5-/spl mu/m rule super self-aligned process technology (SST), 2-/spl mu/m-wide deep U-groove isolation, and a fine 5-/spl mu/m pitch three-level metallization process. The authors describe its process features, cell design, chip structure, experimental results, and applications.