An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC

Abstract

The design of a low-power 10 b, 40 Msample/s ADC integrated in a 0.8 /spl mu/m multithreshold CMOS process is presented. The fully differential design employs parallel-pipelined ADC each using a combination of single- and multibit-per-stage pipelined architectures. The ADC, targeted for high-resolution video terminals and ultrasound scanning applications, achieves a nonlinearity-plus-quantization-error of /spl plusmn/1 LSB at 10 b, dissipates 85 mW from a single 2.7 V supply, and occupies an area of 1.9 mm by 2.1 mm. >