An 82% energy-saving change-sensing flip-flop in 40nm CMOS for ultra-low power applications

Abstract

In this paper, we propose a novel 24-transistor change-sensing flip-flop (CSFF) for ultra-low power applications. With the aid of an internal change-sensing unit, the proposed CSFF eliminates redundant transitions of internal clocked nodes when there is no change in the flip-flop content. No additional transistors are required compared to the conventional transmission-gate flip-flop (TGFF). Measurement results from a test chip fabricated in 40nm CMOS technology show that CSFF achieves the power reduction of 82% and 68% at 10% activity rate and 1.0V, and the C-Q delay improvement of 37% and 11% in the supply voltage range of 0.4V to 1.0V compared to TGFF and SSCFF. While achieving better power and energy efficiencies, CSFF still maintains robust functionality at ultra-low voltage operations. Measurement results also demonstrate that CSFF shows the minimum operating voltage of 0.19 V.