An 8-Bit ROM-Free AES Design for Low-Cost Applications

Ming-Chih Chen,Wei-Ting Li

doi:10.1155/2013/696717

Abstract

We have presented a memory-less design of the advanced encryption standard (AES) with 8-bit data path for applications of wireless communications. The design uses the minimal 160 clock cycles to process a 128-bit data block. For achieving the requirements of low area cost and high performance, new design methods are used to optimize the MixColumns (MC) and Inverse MixColumns (IMC) and ShiftRows (SR) and Inverse ShiftRows (ISR) transformations. Our methods can efficiently reduce the required clock cycles, critical path delays, and area costs of these transformations compared with previous designs. In chip realization, our design with both encryption and decryption abilities has a 29% area increase but achieves 4.85 times improvement in throughput/area compared with the best 8-bit AES design reported before. For encryption only, our AES occupies 3.5 k gates with the critical delay of 12.5 ns and achieves a throughput of 64 Mbps which is the best design compared with previous encryption-only designs.

Highlights

The advanced encryption standard (AES) algorithm has been widely used in data transmission in wireless communications [1,2,3] and radio frequency identification (RFID) applications [4, 5]
The ASIC design of 8-bit AES reported in [5] has the smallest area cost compared with other versions and leads to the lowest performance since more clock cycles are needed in encryption and decryption
The SR/Inverse ShiftRows (ISR) units are implemented by random access memory (RAM)

Summary

Introduction

The AES algorithm has been widely used in data transmission in wireless communications [1,2,3] and RFID applications [4, 5]. The AES design with ASIC chip(s) can achieve the requirements of low cost and high performance. The data path design of AES can be shrunk to 8-bit versions [1, 2, 4,5,6,7, 10, 12, 13] for reducing the area cost. The ASIC design of 8-bit AES reported in [5] has the smallest area cost compared with other versions and leads to the lowest performance since more clock cycles are needed in encryption and decryption. For the objective of reducing the area cost but still keeping the acceptable performance, the proposed AES uses 8-bit data path and minimum clock cycles to perform the encryption/decryption processes

Methods

Results

Conclusion