An 8-bit, 10 KS/s, $$1.87\upmu \text {W}$$ 1.87 μ W Successive Approximation Analog to Digital Converter in $$0.25\,\upmu \hbox {m}$$ 0.25 μ m CMOS Technology for ECG Detection Systems

Abstract

This paper presents an 8-bit successive approximation analog to digital converter (SA-ADC) employing a mostly digital implementation for portable Electrocardiogram (ECG) detection systems. At 10 K samples/s, the proposed SA-ADC consumes $$1.87\,\upmu \hbox {W}$$1.87μW from a 1 V power supply. The layout and extraction of the proposed SA-ADC are done using L-edit and simulated using TSMC $$0.25\,\upmu \hbox {m}$$0.25μm technology file on Pspice. According to the simulation results, the SA-ADC has a signal-to-noise ratio of 57 dB, peak spurious-free dynamic range of 41 dB, and a signal-to-noise-and-distortion ratio of 40.5 dB for a 200 Hz---$$500\hbox {mV}_{\mathrm{pp}}$$500mVpp input sine wave. In addition to that, the SA-ADC has effective number of bits of 6.5-bits, an effective resolution bandwidth of 1.5 kHz and a figure of merit of 6.85 pJ/Conversion step. The digitized ECG signal is precisely reconstructed using a novel reconstruction circuit. These results show that the proposed SA-ADC in $$0.25\,\upmu \hbox {m}$$0.25μm technology is a good candidate for ECG detection systems.