Abstract
This paper presents a method for preventing output level distortion while matching the channel impedance in the single-ended PAM-4 transmitter for memory interfaces. ZQ codes for all four output signal levels were obtained through ZQ calibration and saved in the ZQ code table. The ZQ code generator then adaptively selected the appropriate codes depending on the data pattern and delivered them to the output driver; this can improve the level separation mismatch ratio (RLM) while matching the channel impedance. To validate the effectiveness of our approach, a prototype chip with an active area of 0.035 mm2 was fabricated in a 65 nm CMOS process. It achieved the energy efficiency of 3.09 pJ/bit/pin at 18 Gb/s/pin, and its RLM was 0.971 while matching the channel impedance.
Highlights
The demand for high-bandwidth DRAMs is constantly increasing due to the datacentric trend [1,2,3]
Double data-rate (DDR), low-power double data-rate (LPDDR), and graphic double data-rate (GDDR) memories have a pin count limitation, so a higher clock frequency is required to increase the data-rate per pin
The output signal level deviated from the orating the level separation (RLM) that is a function ofisthe intervals be-ideal level, deteriorating the level separation mismatch ratio (RLM) that is a function of the tween the four PAM-4 output levels
Summary
The demand for high-bandwidth DRAMs is constantly increasing due to the datacentric trend [1,2,3]. DRAM bandwidth can be increased by raising the number of I/O pins or the clock frequency [4]. Double data-rate (DDR), low-power double data-rate (LPDDR), and graphic double data-rate (GDDR) memories have a pin count limitation, so a higher clock frequency is required to increase the data-rate per pin. Since power consumption and frequency-dependent channel loss increases at higher frequencies, it is challenging to increase data transfer speeds using non-return-to-zero (NRZ) signaling. PAM-4 signaling, which can transmit 2 bits per symbol, is more suitable for higher speeds because its clock frequency is only half of that required for NRZ signaling at the same data rate. Further SNR degradation may occur due to the non-linearity characteristics of the transmitter output [8]; this causes an imbalance between PAM-4 signal levels. Since the overall performance depends on the smallest eye height of the transmitter, it is important to equalize the voltage difference between signal levels [8] while matching the channel impedance at each signal level
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