An 11-bit 200MS/s SAR ADC IP for wireless comunacation SOC

Abstract

This paper presents a dual-channel 11-bit 200MS/s hybrid SAR ADC IP. Each channel adopts flash-SAR architecture for high speed, low power and high linearity. Dynamic comparators in the coarse flash ADC and the fine SAR ADC further contribute to the reduction of power consumption. A gate-controlled ring oscillator generates a multi-phase clock for SAR logic, thereby allowing it asynchronously triggers the comparator in the fine SAR ADC in high speed. Post layout simulation concerned noise achieves an ENOB of 10.69 at nyquist input. It consumes 2.718mA at 1.2V supply. Leading to a FOM of 9.86 fJ/conversion-step. The active area of dual channel (I-Q) ADC is 0.35mm2 in a 55nm low leakage CMOS technology.