Abstract
Routing plays an important role in determining the total circuit area and circuit performance and hence must be addressed as early as possible during the design process. In this paper, an effective routing-driven approach for technology-dependent logic synthesis, which relies on alphabetic tree construction, is presented. Alphabetic trees are trees generated under the restriction that the initial order on the leaf nodes is maintained while not introducing any internal edge crossing. First, a mechanism for generating all alphabetic trees on a given number of leaf nodes is presented. Next, the number of such trees is calculated under different height and degree restriction and used to derive upper bounds on the complexity of alphabetic tree optimization problem. A classification of tree cost functions, for which alphabetic trees can be generated in polynomial time, is also proposed. Specifically, alphabetic tree optimization algorithms are applied to generate optimal alphabetic fan-out trees. For fan-out optimization, we obtained 14% improvement in chip area at the cost of 1% loss in performance.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
More From: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.