Abstract
The separation of computing units and memory in the computer architecture mandates energy-intensive data transfers creating the von Neumann bottleneck. This bottleneck is exposed at the application level by the steady growth of IoT and data-centric deep learning algorithms demanding extraordinary throughput. On the hardware level, analog Processing-in-Memory (PiM) schemes are used to build platforms that eliminate the compute-memory gap to overcome the von Neumann bottleneck. PiM can be efficiently implemented with ferroelectric transistors (FeFET), an emerging non-volatile memory technology. However, PiM and FeFET are heavily impacted by process variation, especially in sub 14 nm technology nodes, reducing the reliability and thus inducing errors. Brain-inspired Hyperdimensional Computing (HDC) is robust against such errors. Further, it is able to learn from very little data cutting energy-intensive transfers. Hence, HDC, in combination with PiM, tackles the von Neumann bottleneck at both levels. Nevertheless, the analog nature of PiM schemes necessitates the conversion of results to digital, which is often not considered. Yet, the conversion introduces large overheads and diminishes the PiM efficiency. In this paper, we propose an all-in-memory scheme performing computation and conversion at once, utilizing programmable FeFET synapses to build the comparator used for the conversion. Our experimental setup is first calibrated against Intel 14 nm FinFET technology for both transistor electrical characteristics and variability. Then, a physics-based model of ferroelectric is included to realize the Fe-FinFETs. Using this setup, we analyze the circuit’s susceptibility to process variation, derive a comprehensive error probability model, and inject it into the inference algorithm of HDC. The robustness of HDC against noise and errors is able to withstand the high error probabilities with a loss of merely 0.3% inference accuracy.
Highlights
The recent trend towards data-centric applications, like deep neural networks and big data analysis, challenges the current computer architectures
The variability-induced errors are modeled at circuit level and used at the application level to evaluate the impact on the inference accuracy
An analog Fe-Ternary Content Addressable Memory (TCAM) array XNORs the two inputs, the mismatches are accumulated in analog, and a Fe-Fin Field Effect Transistors (FinFETs)-based synaptic comparator translates the analog result into the digital domain
Summary
The recent trend towards data-centric applications, like deep neural networks and big data analysis, challenges the current computer architectures. A result of this separation between compute and memory units is the “memory wall”. To tackle this problem effectively, advances across the whole technology stack are asked for. Architectures unifying compute and memory units reduce the number of data transfers. Combining these two sides creates an efficient holistic solution. The individual components of such a hypervector can have different data types, such as simple bits, integer, or real numbers. To map complex data into hyperspace, multiple simple value-representing hypervectors are combined with three basic operations. The focus of this work is on binary hypervectors; a comparison of other data types is provided in Schlegel et al (2020)
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