All-Digital ∆Σ TDC with Current-Starved Bi-Directional Gated Delay Line Time Integrator

Abstract

This paper presents an all-digital 1st-order 1-bit ∆Σ time-to-digital converter (TDC) with a differential current-starved bi-directional gated delay line (CS-BDGDL) time integrator with built-in quantization. Current-starved gated delay cells are used to improve the linearity of the time integrator subsequently the SNDR of the TDC. Differential time integration is performed by simultaneously issuing right-shift and left-shift commands to the CS-BDGDL so as to minimize integration time. The error caused by current mismatch between NMOS and PMOS transistors of gated delay cells is eliminated using a digital comparator. Design methodologies for process uncertainty are explored. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show that the figure-of-merit (FOM) of the proposed all-digital TDC outperforms that of all reported TDCs alike.