Algorithms for physical design of ‘sea-of-gates’ chips

Abstract

The paper describes an algorithmic base for the CAD system for physical layout of large sea-of-gates chips. A solution is obtained by successive augmentation of a partial layout. A new, dynamically defined slice is added to the partial solution in each step of the process. Two different techniques are proposed to find candidate cells for inclusion in the slice. Different methods are also proposed for positioning elements inside the slice. Global routing of the partial solution is used to guarantee routability and to direct future placement. The system achieved more than 75% use of the basic cells for two-layer metal CMOS technology with functional cells varying widely in size in both dimensions. It also almost always achieved a 100% completion rate for detailed routing.