Algorithms for arithmetic operation in a systolic array of single-bit processor (SASP)

Abstract

Algorithms for binary integer arithmetic in a Systolic Array of Single-bit Processor (SASP), designed for implementation in wafer scale integration (WSI), are presented. The processing elements (PE), operated in a Single instruction Multiple Data (SIMD) mode, each contains a single-bit arithmetic and logic unit (ALU). The salient feature of the developed algorithms is in the use of the primitive ALU functions to achieve data dependent division arithmetic operational in the SIMD machine. Also, the innovative and efficient algorithmic use of the single-bit ALUs in the SIMD environment makes it possible to realize the full performance of the massively parallel processor. The algorithms are described by a set of programming flow charts. The required sequence of operations in each algorithm are presented according to the actual SASP mnemonics for the operational (OP) codes.