Abstract
It is proposed an algorithm finding the optimal array placement in the distributed memory of a parallel computing system. This work is a step towards the development of a new generation of parallelizing compilers for computing systems with a distributed memory. Such compilers may be useful for manycore systems on chip with addressable local memory (not cache) for each core. This is especially important for systems on chip with a many processor cores, where data exchange with RAM is a performance bottleneck. The construction of special auxiliary program graph for estimation of minimum number of data transfers is obtained. The arrays placement with the optimal number of data transfers is constructing in this paper.
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