Algebraic Series-Parallel-Based Switched-Capacitor DC–DC Boost Converter With Wide Input Voltage Range and Enhanced Power Density

Abstract

This article presents an algebraic series–parallel (ASP) topology for fully integrated switched-capacitor (SC) dc–dc boost converters with flexible fractional voltage conversion ratios (VCRs). By elaborating the output voltage ( ${V} _{\textrm {OUT}}$ ) expression into a specific algebraic form, the proposed ASP can achieve improvements on both the charge sharing and bottom-plate-parasitic losses while maintaining the high topology and fractional VCR flexibility of conventional two-dimensional series–parallel (2DSP) converters. The proposed method consists of a generic ASP topology framework with systematic parameter determination for a precise converter implementation, and can theoretically surpass the power-conversion efficiency (PCE) of 2DSP converters. Fabricated in 65-nm bulk CMOS, we designed a fully integrated ASP-based SC rational boost converter by cascading with the Dickson topology, with a total of seven rational VCRs to boost an input voltage of 0.25–1 V to a 1-V output. Delivering a maximum loading power of 20.4 mW, the chip prototype achieves a peak efficiency of 80% at a power density of 22.7 mW/mm2.