ALD TiN Barrier Metal for pMOS Devices With a Chemical Oxide Interfacial Layer for 20-nm Technology Node

Abstract

We propose the use of atomic layer deposition (ALD) TiN barrier to replace physical vapor deposition TiN barrier for high- k last/gate last pMOS devices with a chemical oxide interfacial layer in 20-nm technology node. It was found that the pMOS devices with ALD TiN exhibit lower gate leakage current density (Jg) and equivalent oxide thickness. Furthermore, it was found that we could achieve larger flat-band voltage (Vfb) and larger equivalent work function from the pMOS devices with ALD TiN barrier. It was also found that we could further improve the performances of the fabricated pMOS devices by increasing the ALD TiN thickness from 2 to 3 nm.