Abstract
Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20 nm-gate transistor. One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies. With 10 nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer and oxide-spacer technologies respectively. Furthermore, the switching energy (power consumption) is reduced by 46% and 33% respectively. The other is SAC process with air spacer. 3D mixed mode simulation shows that the 35% area benefit can be retained while improving the speed and switching energy by 75% to be 10% better than a non-SAC device.
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