Abstract
A vertical structural air channel transistor with a gate block dielectric layer, which can isolate gate from air channel, was proposed. With the presence of gate block dielectric layer, electrons at the edge of the 2-D electron system (2-DES) formed at gate are prevented to be injected into air channel, which may effectively minish the gate leakage current compared to the conventional vertical structure. The transistor operates in the space-charge-limited (SCL) regime of thermionic emission, which makes it theoretically possess the advantages of high-temperature reliability and low power consumption. Simulation results indicate that this transistor can achieve transconductance of 34.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> S and cutoff frequency of 88.2 GHz by optimizing the dimensional parameters.
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