Aggressive Technology and Voltage Scaling (Down to the Subthreshold Domain)

Abstract

The vast majority of the existing studies on GC-eDRAM focus on implementation in mature technology nodes (most often 0.18 μm CMOS and no lower than 65 nm CMOS) and at nominal supply voltages. This chapter studies the suitability of GC-eDRAM beyond these design spaces by analyzing aggressive technology scaling, down to 28 nm CMOS, and aggressive supply voltage scaling, all the way to the subthreshold (sub-VT) domain. First, the analytical retention time model developed in Chap. 3 is validated for a scaled 28 nm CMOS node. Second, a conventional 2T GC topology is optimized for sub-VT operation. Simulations show successful sub-VT operation for a 2T GC-eDRAM array in 0.18 μm CMOS. Furthermore, a 2T GC-eDRAM array implemented in a scaled 40 nm CMOS can be operated successfully down to the near-VT domain, while simultaneous aggressive technology and voltage scaling to the sub-VT domain are not recommended.