Affine Boolean Classification with FPGA Implementation on Secret Image Sharing

Abstract

This paper proposes an (n, n)-threshold secret image sharing (SIS) scheme with equal size in shares that are obtained on affine Boolean classification. The two sets of bit patterns, formed from the fixed and the variable bit positions of this classification, are used to develop the shares. Simplicity in Boolean operations leads to its hardware realization in Field Programmable Gate Array (FPGA) platform using Xilinx ISE design suite 14.5 (device family XC3S700A-4FG484). The proposed SIS scheme shows robustness against various operations including random gain scaling. FPGA architecture, for an 8 bits/pixel ( $8\times 8$ ) secret image, offers a throughput of 133.4 Mbps at frequency of 288.749 MHz.