Abstract
Mask less fabricated 3D interconnects may have a big potential in future microelectronic applications by enhancing freedom of device design or power- and footprint saving capabilities along with performance improvements. Within this paper research activities are reported about evaluation of Aerosol Jet Printing (AJP) for feasibility of fabricating non-planar nano particle based electrical chip interconnects on a 3D-integrated System in a Package (SiP) including MEMS that is capable to wake up integrated electronics from power down mode using piezoelectric MEMS components. 3D-stacked multi-chip modules with a footprint of 9mm x 10mm are functional connected by AJP after single chips are mounted to printed circuit board (PCB) using underfiller adhesives. AJP, morphology of printed paths, and electrical resistances are investigated. Several challenging factors like printed line width, printed layer thickness, focus limiting standoff height of printhead, thermo-mechanical properties of printed interconnects along with SiP layout were identified and discussed during process development.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
