Advantages of Densely Packed Multi-Wire Transistors with Planar Gate Structure Fabricated on Low-k Buried Insulator over Planar Silicon-on-Insulator Devices

Abstract

In this paper, electrical characteristics of densely packed multi wire transistors with a planar gate structure are systematically investigated using three-dimensional device simulations in terms of dependences of threshold voltage roll-off and current drivability on a channel width, height, and distance. The simulation results revealed that densely packed multi wire transistors with a planar gate structure have advantages over planar silicon-on-insulator (SOI) devices in terms of both threshold voltage roll-off characteristics and current drivability. It is shown that narrowing a width and lowering a height of channels are effective for improvement in both threshold voltage roll-off characteristics and current drivability and that shrinking a distance between channels is effective for improvement in current drivability although it degrades threshold voltage roll-off characteristics. It is also shown that lowering a dielectric constant of a buried insulator below wires is effective for improvement in both threshold voltage roll-off characteristics and current drivability of wire transistors.