Advances in flip chip underfill technology for lead-free component packaging

Abstract

Lead containing solders have been employed as an interconnecting and surface coating material in many applications for decades. The two driving forces that affect the present and future requirements of solders for electronic and microelectronic applications are, first, the increased demands on the level of performance due to the increased density and complexity of circuitry and secondly, the concern of the toxicity and health hazard of lead. The second concern has led to government legislation and regulations that have continued to impact the future of lead usage. Extensive literature on lead-free solders has been published in the last decade. A growing area of interest is in lead-free solders for flip chip interconnects. Flip chip interconnections are the electrical and mechanical connections between the semiconductor integrated circuit and the package. These interconnects are formed on the periphery or in an area array on the top surface of an active die. Flip chip interconnects are smaller (of the order of 100 /spl mu/m diameter) than other surface mount joints and are projected to have pitches that shrink to 120 /spl mu/m. The solder joints must withstand board level reflow environments compatible with joining organic substrates that, again, have a maximum reflow temperature of 260/spl deg/C. The lead-free solder must meet these requirements and perform at, or above, the level of performance of the eutectic tin-lead solder alloy it is intended to replace. This paper discusses the design, development , characterization and board level reliability of an advanced flip chip underfill encapsulant using a lead-free alloy (Sn-3.8Ag-0.7Cu) composition as the interconnecting metallurgy. Commonly known as LF2 solder, it has a density of 7.38 g/ml, a liquidus temperature of 217.5/spl deg/C and a solidus temperature of 216.3/spl deg/C. Confocal scanning acoustic microscopy (CSAM) and scanning electron microscopy (SEM) have been employed to study the package microstructure, both before and after reliability. Current work has shown that the assembled flip chip devices have extremely uniform flow fronts in both perimeter array and full area array die. The flow front is seen to be independent of the underfill dispense pattern. The SEM microphotographs have shown uniform distribution of filler particles in the organic phase. The flip chip devices have been subjected to over 3000 cycles of air-to-air thermal cycling (AATC) in the temperature extremes of -55/spl deg/C and 125/spl deg/C with a cycle time of 90 minutes. First electrical failures have been observed after 2500 thermal cycles in the assembled flip chip assemblies. We intend to present the completed reliability studies (Weibull plots) and the associated failure analyses using CSAM, SEM and X-ray techniques. Routes to future work in this area will include the design and development of underfill technology for large, fully populated die with lead-free process compatibility with copper/low-k dielectrics for faster device speed in the front end deep sub-micron technologies.