Abstract
The trend towards larger chip sizes in advanced metal-oxide-semiconductor integrated circuits requires lower and lower gate oxide defect densities. To assess the influence of the starting material and process parameters on the gate oxide defect density, gate oxide test results gathered in connection with 64 and 256 K dynamic random access memories (DRAMS) fabrication are reviewed and compared with data from the literature. A model is proposed according to which a high gate oxide defect density results to a large extent from the synergetic action of grown-in and process-induced microdefects and metal contamination.
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