Advanced techniques for achieving ultra-shallow junctions in future CMOS devices

Abstract

The continued scaling of CMOS devices to the sub-16 nm technology node will likely be achieved with new architectures, such as FinFETs, and new materials, such as high mobility substrates (Ge and/or III-V based). At these technology nodes, abrupt channel doping profiles with high dopant activation will be needed under reduced thermal budget environments. While advanced dopant incorporation and activation techniques continue to be developed for Si scaling, implanting ions into III-V materials presents a fundamental problem as it induces crystal damage, which can alter the stoichiometry in a manner that is difficult to recover. The residual damage can lead to higher junction leakage and lower dopant activation. These challenges require the development of novel junction processing techniques that are inherently defect-free and can be controlled at the nm scale. One such promising technique, monolayer doping (MLD), is reviewed in this article.