Abstract

Uncooled focal plane arrays (FPA) with reduced size, weight, and power consumption (SWaP) features and coupled with enhanced characteristics have the potential to significantly benefit a wide range of imaging applications including space surveillance from terrestrial and space-based platforms and planetary composition mapping for space exploration missions. Recently, an innovative, uncooled Photon-Sensing Integrated Circuit (PSIC) hetero-junction phototransistor (HPT) device has been developed. This InGaAs based PSIC HPT device is a room temperature detector and imager that is of 320 x 256 pixel format with 30 micron pixels, and operates in the short-wave infrared (SWIR) spectral region of 0.9 to 1.7 microns. It is a continuously operating (i.e., zero recovery time), zero-excess-noise and linear-mode (i.e., capable of representing photon numbers) photon-sensing detector and imager. Enabled by its hetero-junction phototransistor (HPT) amplification instead of the conventional avalanche multiplication mechanism, this InGaAs HPT simultaneously exhibits signal amplification gain of >1000, namely, >20 x higher gain, and <1/10 lower dark current areal density than InGaAs avalanche photodiode (APD). The photon transfer data (relationship between signal, noise and photon number) for this PSIC imager at FPA mean value and at room temperature is approximately 0.2 noise-equivalent photons per pixel per frame measured using a readout Integrated circuit (ROIC) with 350-700 electron readout noise. The measured uncooled specific detectivity, D* of 3E14 cm.Hz/W appears to be higher than those available commercially. The current HPTs exhibit higher speed, higher gain, lower dark current and noise, and hence achieve highest signal-to-noise ratio (SNR) for photon detection. Recently, the prototype device was selected for space qualification studies on the international space station (ISS). Under NASA’s MISSE-11 (Materials International Space Station Experiment) mission, this device was integrated on to a carrier with various other test components and was launched in April 2019. In this paper, salient features of material processing, device configuration and packaging architecture followed by the pre-flight performance tests carried out will be presented.

Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call