Advanced plasma technology in microelectronics

Abstract

The current status and future trends of plasma technology for microelectronics are discussed. The low pressure high density plasma (HDP) source is advantageous for the etching of a gate electrode and a small deep contact hole. However, the high temperature electrons in the HDP may induce profile defects, notch and sidewall etching, and may degrade the electrical quality of the gate oxide. By lowering the electron temperature with the pulse plasma technique, the etch profile of the gate electrode was improved. Platinum, the suggested storage electrode for the capacitor of the next generation ULSI, was etched in a magnetically enhanced reactive ion etching (MERIE) plasma. With the etching chemistry of Cl 2/O 2/Ar, it was etched with the slope of up-to 80°. In SiO 2 etching, the HDP is advantageous for less RIE-lag. We also need to control the polymerization for the critical dimension (CD) control and for the selectivities to the resist, silicon, and also to Si 3N 4 for the self-aligned contact (SAC). It was shown that it is possible to control the dissociation of radicals in the plasma and the surface reaction with a phase-controlled pulse plasma. The chemistry C 4F 8/CH 3F/Ar was shown to achieve the requirements for the SAC hole etching, but the process window was quite narrow. Also, the HDP-CVD SiO 2 and SiOF have shown better gap filling capability, film quality and more favorable deposition profiles than conventional CVD oxides. We also discussed the results of the application of HDP-CVD oxide to the trench isolation and the intermetal dielectrics (IMDs). The film characteristics of fluorine doped HDP-CVD SiO 2 (SiOF) as a low dielectric material was found to be very stable with uniform film properties even after high temperature stressing at 350°C for 100 h.