Abstract
The multilevel cell (MLC) technology was initially developed for MLC (2 bits/cell), but it was extended to TLC (3 bits/cell) and QLC (4 bits/cell). MLC technology has been developed to focus on the operations of making narrow V t distribution width. A lot of sophisticated techniques have been proposed and implemented to a NAND flash memory product. This chapter first describes these techniques, such as the incremental step pulse program (ISPP), bit-by-bit verify operations, a two-step verify scheme, and a pseudo-pass scheme. It then discusses several page program sequences to reduce the effect of floating-gate capacitive coupling. The chapter also describes TLC (3 bits/cell) and QLC (4 bits/cell) technologies. Next, the three-level cell technology is introduced to compromise the performance and reliability of single-level cell (SLC) and MLC. Finally, the moving read algorithm is presented to compensate a V t shift for minimizing a bit failure rate.
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