Abstract
The multilevel cell (MLC) technology was initially developed for MLC (2 bits/cell), but it was extended to TLC (3 bits/cell) and QLC (4 bits/cell). MLC technology has been developed to focus on the operations of making narrow V t distribution width. A lot of sophisticated techniques have been proposed and implemented to a NAND flash memory product. This chapter first describes these techniques, such as the incremental step pulse program (ISPP), bit-by-bit verify operations, a two-step verify scheme, and a pseudo-pass scheme. It then discusses several page program sequences to reduce the effect of floating-gate capacitive coupling. The chapter also describes TLC (3 bits/cell) and QLC (4 bits/cell) technologies. Next, the three-level cell technology is introduced to compromise the performance and reliability of single-level cell (SLC) and MLC. Finally, the moving read algorithm is presented to compensate a V t shift for minimizing a bit failure rate.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.