Abstract
This study examines several possible back-end-of-line process options for future leading edge, high performance semiconductor devices, discussing effects on electrical and reliability characteristics as well as specific processing challenges. The extendibility of current physical vapor deposition-based processes for barrier layers, based on existing tool sets and therefore representing the most cost-efficient solution, is reviewed. Subsequently, alloying options such as Cu(Mn) in the seed are highlighted, showing excellent reliability, but also leading to challenges with electrical performance. Furthermore, the applicability of atomic layer and chemical vapor deposition processes for barrier applications and their limits are examined. The electromigration advantage of selective metallic capping processes such as electroless cobalt–tungsten–phosphorus deposition and chemically-vapor-deposited cobalt is highlighted, while process challenges are shown. Additionally, the need for careful adjustment of the Cu plating process and evaluation of electromigration performance upon changes to the barrier/liner/seed process is discussed.
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