Abstract
In this paper, we propose two sub 0.5 μm i-line processes (0.40 NA stepper), for negative and positive patterning, using the same acid hardening resist: the negative patterning is achieved via wet development and the positive patterning via silylation and dry development. We first considere the wet development negative process. Such a negative process is strategic for many lithographic levels, and we here demonstrate its application for sub 0.5 μm gates fabrication [the level of IC fabrication requiring the highest resolution]. The lithographic results obtained over flat and topographic polysilicon wafers are presented and discussed in terms of exposure dose and focus latitudes. The plasma etching behavior of the resist is then studied and discussed as a function of the gas chemistry: the best conditions are finally used for transfering the patterns into a 0.38 μm thick polysilicon layer. In the second part of this paper, we demonstrate a positive dry development process using vapor silylation; different silylation conditions and development modes are evaluated. Such a process could be used where regular wet development processes reach their limits, or where a positive process is better adapted to the geometry of the level in fabrication: only one resist would then be necessary for both polarities.
Published Version
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