Advanced gate stacks with fully silicided (FUSI) gates and high-k dielectrics. enhanced performance at reduced gate leakage

Evgeni Gusev ,J Newbury,V Narayanan,Y Zhang,A Callegari ,M Gribelyuk ,Paul Kozlowski ,Hasan M Nayfeh ,R Amos ,R Carruthers ,D Latulipe ,N A Bojarczuk ,Vamsi Paruchuri ,C Cabral ,M Steen ,Kai-Wei Ku ,An Steegen ,K Maitra ,Martin M Frank ,Supratik Guha ,R Jammy ,M Copel ,R Rengarajan ,B.p Under ,Stephen A Cohen ,M Ieong ,G Shahidi ,Y.h Kim ,J Kedzierski ,G Biery ,D Lacey ,P Jamison ,S Fang ,Sufi Zafar ,P Nguyen ,H.c Ng

doi:10.1109/iedm.2004.1419071

Advanced gate stacks with fully silicided (FUSI) gates and high-k dielectrics. enhanced performance at reduced gate leakage

Evgeni Gusev , J Newbury + Show 34 more

https://doi.org/10.1109/iedm.2004.1419071

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Publication Date: Dec 13, 2004

Citations: 27

Affiliation: IBM (United States)

#Spl Sim #Fully Silicided + Show 8 more

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Abstract

The key result in this work is that FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant gate leakage reduction (due to high-/spl kappa/) and drive current improvement at T/sub inv/ /spl sim/ 2 nm (due to: (i) elimination of poly depletion effect, /spl sim/ 0.5 nm, and (ii) the high mobility of HfSi/sub x/O/sub y/). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)/spl sim/ -0.4 V and Vt(NFET) /spl sim/ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V/sub t/ stability) was found in the case of NiSi/ HfSi/sub x/O/sub y/ compared to the same gate electrode with HfO/sub 2/ dielectric.

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