Advanced Encryption Standard with Galois Counter Mode using Field Programmable Gate Array.

Abstract

Nowadays, the protection of transferring data is important to prevent the data hack easily. Advanced Encryption Standard with Galois Counter Mode (AES-GCM) plays an important role to provide high assurance of authenticity and data confidentiality in electronics, computers and other communication applications. This paper presents the implementation of AES-GCM by using Field Programmable Gate Array (FPGA) and AES-GCM designs in parallel-pipelined to achieve high performance in term of throughput and latency. The implementation of AES-GCM in FPGA by using 128-bit of input data block, Initialization vector (IV) and Additional Authenticated Data (AAD) to provide a high speed of authenticated encryption / decryption. The key length of AES-GCM is 256-bit to provide the high security system and the operation of key expand designed in parallel to optimize operation time of AES-GCM. The proposed architecture is designed in Verilog hardware description language (HDL) and implemented using DE1-SoC with Cyclone V device. A parallel-pipelined of AES-GCM is introduced and it is operated at 10 MHz, achieved throughput of 16.84 Gbps, utilized of 11,196 slices. AES-GCM is carried out with the key-length of 256-bit is suitable to perform at high speed of electronic applications in term of security.