Abstract
A new SRAM cell with better leakage control and enhanced memory retention capability is proposed. The memory array configured using the proposed SRAM cell has all its word lines and bit lines driven adiabatically using differential cascode and pre-resolved adiabatic logic (DCPAL), and it operates as a buffer for the memory array. This paper demonstrates how one of major concerns, namely, the VT variation can be controlled by modifying the ground-line and power-line voltage of the SRAM cell. The designs are implemented using 45-nm technology models operating at a supply voltage of 0.8 V.
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