Abstract

In current systems, memory accesses to a DRAM chip must obey a set of minimum latency restrictions specified in the DRAM standard. Such timing parameters exist to guarantee reliable operation. When deciding the timing parameters, DRAM manufacturers incorporate a very large margin as a provision against two worst-case scenarios. First, due to process variation, some outlier chips are much slower than others and cannot be operated as fast. Second, chips become slower at higher temperatures, and all chips need to operate reliably at the highest supported (i.e., worst-case) DRAM temperature (85° C). In this paper, we show that typical DRAM chips operating at typical temperatures (e.g., 55° C) are capable of providing a much smaller access latency, but are nevertheless forced to operate at the largest latency of the worst-case. Our goal in this paper is to exploit the extra margin that is built into the DRAM timing parameters to improve performance. Using an FPGA-based testing platform, we first characterize the extra margin for 115 DRAM modules from three major manufacturers. Our results demonstrate that it is possible to reduce four of the most critical timing parameters by a minimum/maximum of 17.3%/54.8% at 55°C without sacrificing correctness. Based on this characterization, we propose Adaptive-Latency DRAM (AL-DRAM), a mechanism that adoptively reduces the timing parameters for DRAM modules based on the current operating condition. AL-DRAM does not require any changes to the DRAM chip or its interface. We evaluate AL-DRAM on a real system that allows us to reconfigure the timing parameters at runtime. We show that AL-DRAM improves the performance of memory-intensive workloads by an average of 14% without introducing any errors. We discuss and show why AL-DRAM does not compromise reliability. We conclude that dynamically optimizing the DRAM timing parameters can reliably improve system performance.

Highlights

  • A DRAM chip is made of capacitor-based cells that represent data in the form of electrical charge

  • This is the first work to (i) provide a detailed qualitative and empirical analysis of the relationship between process variation and temperature dependence of modern DRAM devices on the one side, and DRAM access latency on the other side, (ii) experimentally characterize a large number of existing DIMMs to understand the potential of reducing DRAM timing constraints, (iii) provide a practical mechanism that can take advantage of this potential, and (iv) evaluate the performance benefits of this mechanism by dynamically optimizing DRAM timing parameters on a real system using a variety of real workloads

  • This paper introduces Adaptive-Latency DRAM (AL-DRAM), a simple and effective mechanism for dynamically tailoring the DRAM timing parameters for the current operating condition without introducing any errors

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Summary

Introduction

A DRAM chip is made of capacitor-based cells that represent data in the form of electrical charge. When a DRAM chip is accessed, it requires a certain amount of time before enough charge can move into the cell (or the bitline) for the data to be reliably stored (or retrieved) To guarantee this behavior, DRAM manufacturers impose a set of minimum latency restrictions on DRAM accesses, called timing parameters [25]. Timing parameters prescribed by the DRAM manufacturers are dictated by the worst-case cells (the slowest cells) operating under the worst-case conditions (the highest temperature of 85◦C [25]) Such pessimism on the part of the DRAM manufacturers is motivated by their desire to (i) increase chip yield and (ii) reduce chip testing time. Compared to the worst-case cell operating at the worst-case temperature (85◦C), a typical cell at a typical temperature allows much faster movement of charge, leading to shorter access latency This enables the opportunity to reduce timing parameters without introducing errors. For a wide variety of memory-intensive workloads, AL-DRAM improves system performance by an average of 14.0% and a maximum of 20.5% without incurring errors

DRAM Organization
DRAM Operation
Charge Gap
Process Variation
Temperature Dependence
Reliable Operation with Shortened Timing
Adaptive-Latency DRAM
Identifying the Best Timing Parameters
Enforcing Dynamic Timing Parameters
Profiling Infrastructure
Profiling Mechanism
DRAM Latency Profiling Results and Analysis
Effect of Reducing Individual Timing Parameters
Effect of Reducing Multiple Timing Parameters
Effect of Temperature on Timing Slack
Potential Timing Parameter Reductions While Maintaining the Safety-Margin
Effect of Process Variation on Timing Slack
Analysis of the Repeatability of Cell Failures
Real-System Evaluation
Tuning the Timing Parameters
Performance Improvement
Reliability of Reduced Timing Parameters
Rank 2 Channel 2 Rank 2 Channel
Sensitivity Analysis
Related Work
Findings
10. Conclusion
Full Text
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