Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches

Abstract

Domain wall memory (DWM), also known as racetrack memory, is gaining significant attention for embedded cache application due to low standby power, excellent retention, and the ability to store multiple bits per cell. In addition, it offers fast access time, good endurance, and retention. However, it suffers from poor write latency, shift latency, shift power, and write power. In addition, we observe that process variation can result in a large spread in write and read latency variations. The performance of conventionally designed DWM cache can degrade as much as 13% due to process variations. We propose a novel and adaptive write current and shift current boosting to address this issue. The bits experiencing worst case write latency are fixed through a combination of write and shift boosting, whereas worst case read bits are fixed by shift boosting. Simulations show a 30% dynamic energy improvement compared with boosting all bit-cells and a 18% performance improvement compared with worst case latency due to process variation over a wide range of PARSEC benchmarks.