Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support

Abstract

The requirements for a processor, in terms of its characteristics such as RISC (Reduced Instruction Set Computer), CISC (Complex Instruction Set Computer), bitwidth, instruction set, and for the communication and memory bandwidth differ for each application to be implemented. Furthermore, the required characteristic can be different at runtime, because the application has to react to the demands of the environment. Image processing is a good example for this scenario, because this application domain needs to adapt, depending on the content of the camera frames. Integrated, e.g., in a robot, the time variant requirements for the image processing applications are obvious. Sometimes gestures, obstacles, moving targets, etc. need to be detected within a high-resolution picture obtained by one or more cameras. For such applications, a novel Runtime Adaptive Multi-Processor System-on-Chip (RAMPSoC) was invented to provide an adaptive hardware architecture at design- and at runtime. This way, new degrees of freedom in system design and runtime support are provided. To program such a flexible multiprocessor system, an efficient design methodology is of high importance to hide the complexity of the underlying hardware. In addition, a runtime operating system is needed to handle the resource management and the runtime scheduling of the applications. In this chapter, the hardware architecture, the design methodology, and the runtime operating system of RAMPSoC are described. Furthermore, a brief overview about reconfigurable computing and dynamic and partial reconfiguration are given.