Adaptive logic circuits

Abstract

1,020,964. Learning circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 30, 1964 [Oct. 28, 1963], No. 39736/64. Heading G4R. [Also in Division H3] An adaptive logic circuit consisting of a transistor latch and a core is capable of assuming a stable state when an input signal and a conditioning signal are applied to it and produces an output when a further input is applied. The circuit AM1, Fig. 1b, has an input A and a conditioning input CU10. If one or the other only is energized the circuit is not affected. But if both are energized, the currents are summed in lamp AM1L and, via core winding 9, raise the emitter voltage of transistor TR6 above the base voltage ETH so that it cuts off. This causes the emitter voltage of transistor TR8 to rise and this transistor conducts holding transistor TR6 cut off. The conduction of transistor TR8 passes current through coil 5 to set the core. If the power supply should fail the latch will reset but the core remains set. If when power returns the M-SET key is pressed the charge on a capacitor Q1 is passed through coil 7 to reset the core. In resetting the core induces a pulse in coil 9 which sets the latch to previous condition i.e. with TR6 off and TR8 on, the core being set again by the current in core 5. The circuit is reset by switch M-RESET operated at the same time as switch M-SET. As before the charge on capacitor Q1 resets the core but the rising induced voltage at the emitter of transistor TR6 no longer holds this transistor non-conducting because the collector is now disconnected from earth and the base of transistor TR8 is also disconnected from earth. The latch therefore resets to the condition in which TR6 conducts and TR8 is off. Capacitor Q1 is charged by a circuit comprising transistors TR14 and TR16 acting as a latch. When the latch is off the capacitor Q1 charges through diode D37 and resistor R47. After switch MSET is operated to discharge capacitor Q1 the anode of diode D37 is at earth potential and current flows through the diode raising the potential of the function between resistor R47 and R45 and causing the latch to be set. When set transistor T14 conducts to raise the voltage at its collector and back-biasing diode D37 to act off the charging current to the capacitor. The capacitor is recharged when the latch is reset by operation of switch M-RESET or by removal of the power. The latch therefore acts as an interlock ensuring that the switches M-SET and M-RESET are operated alternately. The logic circuits form part of a system, Figs. 1a, 1b in which a combination of three binary signals applied by switches AK, BK, and CK and stored on transistor triggers AKT, BKT, and CKT. Mark and space outputs from each trigger are gated together in gates &EF1- &EF8, one for each possible combination, to produce an output on one of the eight leads A, B &c. These serve as the input to sixteen logic units arranged in two groups of eight. The first group is conditioned by closing switch XCK and the second by switch YCK. The input and the conditioning signals are summed in lamp AM1L as described to set the logic circuit AM1. After the circuits have all been set the conditioning switch CON is opened. Lamps AM1L indicate which circuits are set. In the subsequent operation of the circuit the input on leads A, B &c. produce outputs AM10 from the circuits which have been set, diodes D8 being back-biased by conduction of transistors TR8. The outputs from the two groups of logic circuits are Or-gated together as shown in unit YOM and cause a lamp XL or YL to be lit. The input combinations are thereby classified during the "learning" phase into two classes and during the recognition phase the class is indicated by illumination of one of two lamps.