Abstract
The conventional linear address map can degrade memory utilization and system performance when an access pattern is not linear. To improve memory system performance, the adaptive bank-interleaved linear address map for a DRAM technology is proposed. In our approach, the addresses are efficiently rearranged using the bank-flipping technique for a given application and a memory configuration. The system can configure the address map based on the bank interleaving metric in the systematic way when an application is invoked. Considering image processing applications, the algorithm, the analysis, the design, and the evaluation of the proposed address map are presented. The experimental results show that the presented method can effectively improve the performance with a moderate hardware cost.
Highlights
A modern system on a chip (SoC) increasingly embeds high bandwidth image processing components together with high resolution displays and cameras
The interface of a component operates with AXI bus protocol [21]
To evaluate the performance of the presented address map, the cycle-based transaction-level performance model is implemented in C++
Summary
A modern system on a chip (SoC) increasingly embeds high bandwidth image processing components together with high resolution displays and cameras. If the memory access pattern of an application is linear, high utilization can be maintained in a DRAM. This is because bank conflicts are minimized. The design method to adapt an address map to various memory maps is presented, whereas only the fixed row-bank-column (RBC) map is considered in [1]. In our work, using the legacy OS allocator, a hardware rearranges an address layout when an application is invoked and bank conflicts are expected. The customized address map for bank-level parallelism in a DRAM is presented. Our work differs from [14] in that an addressing scheme to exploit the characteristics of DRAM banks is presented.
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